This invention relates to a digital phase-locked loop (PLL) circuit for use in a signal demodulation circuit, etc., which generates a synchronization signal in synchronization with an input signal.
A conventional PLL circuit is shown in FIG. 1 which generates a signal in synchronization with an input signal during a serial data transmission.
In this PLL circuit, programmable counter 1 receives and frequency-divides a reference clock pulse of a frequency substantially N times (N: an integer) the frequency of an input signal In to produce a synchronization signal. Phase detector or phase comparator 2 detects a phase difference between the synchronization signal and input signal to allow the preset value of up/down counter 3 to be incremented or decremented so that the frequency division ratio of programmable counter 1 may be varied. Where the input signal is phase-advanced ahead of the synchronization signal, the frequency division ratio is made smaller to advance the phase of the synchronization signal. Where, on the other hand, the input signal is phase-delayed behind the synchronization signal, the frequency division ratio is made greater to delay the phase of the synchronization signal.
In the conventional PLL circuit, the phase of the synchronization signal varies in units of 2.pi./N radians and, in order to obtain a minute phase difference or time resolution, it is necessary to enhance the frequency of the reference clock and thus make the value of N greater. A programmable counter and an associated input circuit are thus required to perform a high-speed operation. However, the high-speed operation is restricted in the programmable counter and it is therefore difficult to implement a programmable counter of such a type as to satisfy the requirement for a high-speed operation. Since, even if the phase of the input signal substantially coincides with that of the synchronization signal, that is, the phase difference is set within a range of .+-.2.pi./N, a fluctuation occurs by the phase of .+-.2.pi./N radians, and it is difficult to obtain a stable synchronization signal.